ON Semiconductor 4569 free download

File name 4569.pdf

MC14569B Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter The MC14569B is a programmable divide­by­N dual 4­bit binary or BCD down counter constructed with MOS P­channel and N­channel enhancement mode devices (complementary MOS) in a monolithic structure. This device has been designed for use with the MC14568B phase comparator/counter in frequency synthesizers, phase­locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14569BCP AWLYYWW 1 16 TSSOP­16 DT SUFFIX CASE 948F 1 16 14 569B ALYW · Speed­up Circuitry for Zero Detection · Each 4­Bit Counter Can Divide Independently in BCD or Binary · · · Mode Can be Cascaded With MC14526B for Frequency Synthesizer Applications All Outputs are Buffered Schmitt Triggered Clock Conditioning MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V SOIC­16 DW SUFFIX CASE 751G 1 14569B AWLYYWW mA mW °C °C °C A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC14569BCP MC14569BDT MC14569BDW MC14569BDWR2 Package PDIP­16 TSSOP­16 SOIC­16 SOIC­16 Shipping 2000/Box 96/Rail 47/Rail 1000/Tape & Reel 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14569B/D MC14569B PIN ASSIGNMENT ZERO DETECT CTL1 P0 P1 P2 P3 CASCADE FEEDBACK VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q P7 P6 P5 P4 CTL2 CLOCK BLOCK DIAGRAM P0 P1 P2 P3 CTL = Low for Binary Count CTL = High for BCD Count 3 4 5 6 CTL1 CTL2 2 10 P4 P5 P6 P7 11 12 13 14 VDD = PIN 16 VSS = PIN 8 15 Q CLOCK 9 BINARY/BCD COUNTER #1 CLOCK LOAD BINARY/BCD COUNTER #2 CASCADE 7 FEEDBACK ZERO DETECT ENCODER 1 ZERO DETECT http://onsemi.com 2 MC14569B ООООООООООООООООООООООООООООООООО ООООООООООООООООООООООООООООООООО ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL